To increase the number of devices on semiconductor chips, efforts have been made over a long period of time to build semiconducting devices other than at the surface of the chip. For example, capacitors for 4 megabit and higher memory chips are currently in production either in stacks above the silicon surface or in trenches below. Vertical multi-junction solar cells have pn junctions in grooves etched deeply into the silicon. Field effect transistors (FETs) have also been stacked as described hereinbelow.
With respect to trench capacitors, significant progress has been made to increase the surface area of the trench. Deep vertical trenches and derivatives from vertical trenches, such as crystallographic orientation dependent etches and horizontal trench etches, all add capacitor surface area without using up additional chip surface area. For example, commonly assigned U.S. Pat. No. 4,397,075 to Fatula, Jr. et. al., describes a capacitor with increased surface area achieved by crystallographic etch within a trench. A paper by D. L. Kendall in "Applied Physics Letters," Vol. 26, No. 4, Feb. 15, 1975 p. 195 (the "Kendall paper"), describes orientation dependent etches for forming narrow vertical grooves in silicon suitable for capacitors and vertical multi-junction solar cells. U.S. Pat. No. 5,068,199 to Sandhu (the "'199 patent") describes a capacitor with increased surface area achieved by the use of porous silicon. Commonly assigned U.S. Pat. No. 5,160,987 to Pricer (the "'987 patent"), and U.S. Pat. 4,763,179 to Tsubouchi et al. (the "'179 patent"), describe capacitors with increased surface area achieved by forming horizontal trenches from a standard vertical trench.
In the '987 patent, the buried horizontal trenches of the capacitor are formed by dopant concentration preferential etching of a plurality of lightly doped layers located between heavily doped layers of polysilicon or single crystal silicon. The single crystal layers are formed by a series of chemical vapor depositions performed in ultra high vacuum (UHV-CVD) at low temperature. In the '179 patent, a single buried horizontal trench is formed by an isotropic silicon etch at the exposed bottom of a trench provided with coated walls. However, with isotropic etching vertical etching is extensive and the horizontal trench so formed is much wider than trenches formed with an orientation dependent etchant. In fact, the isotropically etched trench is almost round in shape.
While the process of forming a buried horizontal trench by means of the etching of alternately doped regions provides means for increasing capacitance as described in the references mentioned hereinabove, processes previously disclosed have not been suitable for stacking FETs. The problem with applying some of these processes in the fabrication of FETs is that the lightly doped regions are etched more rapidly than the heavily doped regions. Practical FETs and other active devices cannot be formed in the heavily doped regions remaining after the etch.
However, a paper by H. Horie et al "A New SOI Fabrication Technique for ultrathin Active Layer of Less than 80 nm," published by the IEEE in the 1990 Symposium on VLSI Technology describes an etchant that preferentially attacks n+ silicon, such as a solution of HF, HNO3, and CH3COOH at a 1/3/8 ratio and can be used to hollow-out an n+ layer, forming a horizontal trench.
Horizontal trenches have also been used for improved isolation as exemplified by U.S. Pat. No. 5,112,771 to Ishii et al. (the '"771 patent") and in the disclosure "Total Dielectric Isolation," by B. M. Kemlage, et. al., IBM Technical Disclosure Bulletin, Vol. 24, no. 110, April 1982 (the "Kemlage paper"). In the '771 patent, a process is disclosed for forming a horizontal trench by a method similar to that described hereinabove for the '179 patent. The Kemlage paper describes a process for forming a horizontal trench at the exposed bottom of a vertical trench with coated walls formed in a substrate with a &lt;111&gt; orientation by a highly selective crystallographic orientation dependent etch.
U.S. Pat. No. 4,685,198 to Kawakita et al. provides full oxide isolation by thermally oxidizing under a device region from adjacent vertical trenches with protected sidewalls that have been sideways crystalographically etched. However, the etch does not appear to form horizontal trenches.
In another embodiment in the '987 patent, horizontal trenches are used for the formation of a stack of memory cells, each comprising a polysilicon capacitor and a polysilicon diode transfer device. The horizontal trenches are formed by preferentially etching layers of polysilicon separated by layers of insulator. However, there are two problems with the stack of memory cells described in the '987 patent. First, a diode transfer device formed in polysilicon is much inferior to a transistor in single crystal silicon. Second, the surface area and capacitance of each horizontal trench are smaller than that of a vertical trench if the structures are to be tightly packed on a chip.
With respect to transistor stacking, significant effort has gone into providing a second surface of silicon for device fabrication. This second surface provides the surface on which the second in a stack of two transistors is formed.
In one line of work, stacked CMOS invertor structures are built in which p-channel and n-channel devices share a gate, with one built in single crystal below the gate, the other built in polysilicon on top of the gate. For example, in U.S. Pat. No. 4,272,880 to Pashley, an invertor circuit is fabricated using multilayer integrated circuit processing. Another multilayer arrangement is illustrated in U.S. Pat. No. 4,240,097 to Raymond. However, carrier mobility in polysilicon is significantly lower than mobility in single crystal silicon, and so switching time for the upper device is longer. As will be seen below, because the two devices are formed in sequence, the lower device, although formed in single crystal, also suffers performance degradation.
In a related approach, the second surface of silicon is formed as single crystal silicon, either by epitaxial overgrowth or by recrystallizing the deposited polysilicon with a laser, electron beam, or snip heater. For example, commonly assigned U.S. Pat. No. 4,603,341 to Bertin, et. al. describes a method of forming a stack of transistors for a read only memory in which polysilicon on the second layer is recrystallized to form single crystal silicon by laser annealing. These methods overcome the limitations of polysilicon, but overgrowth and recrystallization efforts have still only had limited success.
In all the stacking methods so far discussed, it is believed that transistors at each level are formed sequentially. The lowest level of transistors are formed first, then the next layer of silicon is deposited and transistors are formed on that level. The steps are repeated for each succeeding level. Because some of the steps, such as gate oxidation, require elevated temperatures that drive dopants deeper, lower level transistors are exposed to a significantly higher thermal budget than higher level transistors. Dopants at the lower levels are therefore driven significantly deeper, seriously degrading lower level transistor performance. This problem cannot be cured by improvements in the quality of deposited or recrystallized polysilicon unless improvements reducing thermal budget are found.
Recently issued, and commonly assigned U.S. Pat. No. 5,319,240, (the '"240 patent") to Faure et al., discloses a stack of FETs formed simultaneously in horizontal trenches in alternately doped layers of UHV-CVD single crystal silicon. Channel regions are formed of unetched p- bulk single crystal silicon and the gates are formed of polysilicon deposited within the horizontal trenches. Source and drain regions and connectors thereto are diffussed from doped oxide adjacent to the channel. This poses a problem since the connectors must be as narrow as the source and drain diffusions. Thus, device series resistance is traded off against device overlap capacitance, and performance is significantly degraded compared to standard surface devices (in which source and drain connectors are formed separately from diffusions and can therefore use higher conductance layers). The '240 patent discloses horizontal trenches formed by dopant concentration preferential etching in which the etchant stops on p+ silicon, and in which, under proper bias conditions the etchant continues to etch n doped silicon and stops on p-silicon. These p+ layers may be completely oxidized. Thus, substantially continuous p+ layers or oxidized residues of p+ layers are left adjacent or sandwiching each device and horizontal trench. These p+ layers or oxidized residues of p+ layers add to the vertical dimension of each device and interfere with forming devices sharing a gate. Thus, the prior art describes techniques for forming trenches to increase capacitance and improve electrical isolation; for building stacks of polysilicon memory cells with diode transfer devices; for forming a second layer of silicon for stacking transistors either in polysilicon or in single crystal silicon formed by overgrowth or recrystallization; and for simultaneously forming stacks of FETs that have substantially continuous p+ layers adjacent or sandwiching each device and that have high resistance diffused connectors to source and drain.
It is believed that the prior art has failed to provide a method of forming horizontal trenches suitable for FETs and other 3-terminal devices by means of preferentially etching heavily doped p regions instead of heavily doped n regions or lightly doped regions. Nor is it believed that the prior art provided means to wire between the electrodes of simultaneously formed subsurface transistors to form a stack of invertors. Nor is it believed that the prior art provided means to wire between a specific subsurface electrode and another in a stack of devices formed in other than sequentially deposited layers of silicon. Furthermore, the prior art apparently has not provided means for overcoming the performance degradation of the lower level transistors in a sequentially deposited stack of transistors or the connector related performance degradation in all of the transistors of a simultaneously formed stack of transistors.